Fix PCIe Gen 3 on CM5: custom DT overlay for missing pciex1 alias

The CM5 DTB (bcm2712-rpi-cm5-cm5io.dtb) lacks the pciex1 alias that
the Pi 5 DTB provides, making dtparam=pciex1_gen=3 silently fail.

Add a custom device tree overlay (pcie-gen3.dtbo) that targets
/axi/pcie@1000110000 directly to set max-link-speed = <3>. The overlay
is embedded in the SBC installer and written to /boot/EFI/overlays/
during install/upgrade.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

Makefile

@@ -124,7 +124,8 @@ patches-overlay:
 		else \
 			echo "Overlay Go $$GO_VER — skipping Go toolchain patch (CVEs fixed upstream)"; \
 		fi && \
-		git am "$(PATCHES_DIRECTORY)/talos-rpi5/sbc-raspberrypi5/0002-"*.patch
+		git am "$(PATCHES_DIRECTORY)/talos-rpi5/sbc-raspberrypi5/0002-"*.patch && \
+		git am "$(PATCHES_DIRECTORY)/talos-rpi5/sbc-raspberrypi5/0003-"*.patch
 
 patches: patches-pkgs patches-talos patches-overlay
 

config/config.txt

@@ -17,9 +17,10 @@ enable_uart=1
 # The debug UART (ttyAMA10) is always active regardless of this setting.
 [pi5]
 enable_uart=0
-# Enable PCIe and force Gen 3 for NVMe (~800 MB/s vs ~400 MB/s Gen 2)
+# Enable PCIe Gen 3 for NVMe (~800 MB/s vs ~400 MB/s Gen 2)
-dtparam=pciex1
+# CM5 DTB lacks the pciex1 alias needed for dtparam=pciex1_gen=3,
-dtparam=pciex1_gen=3
+# so we use a custom overlay that targets pcie@1000110000 directly.
+dtoverlay=pcie-gen3
 [all]
 # Disable Bluetooth.
 dtoverlay=disable-bt

patches/talos-rpi5/sbc-raspberrypi5/0003-Add-PCIe-Gen-3-overlay-for-CM5.patch

@@ -0,0 +1,66 @@
+From b7b424db9b0f771c60c4090c30bf1246eeef6995 Mon Sep 17 00:00:00 2001
+From: Mathias Beaulieu-Duncan <mathias@openharbor.io>
+Date: Mon, 16 Feb 2026 19:07:45 -0500
+Subject: [PATCH] Add PCIe Gen 3 overlay for CM5
+
+The CM5 device tree (bcm2712-rpi-cm5-cm5io.dtb) lacks the pciex1 alias
+that the Pi 5 DTB provides, making dtparam=pciex1_gen=3 silently
+non-functional on CM5 boards.
+
+This adds a custom device tree overlay (pcie-gen3.dtbo) that targets
+/axi/pcie@1000110000 directly to set max-link-speed = <3>, bypassing
+the missing alias entirely. The overlay is embedded in the installer
+binary and written to /boot/EFI/overlays/ during install/upgrade.
+
+Combined with dtoverlay=pcie-gen3 in config.txt, this enables PCIe
+Gen 3 (8.0 GT/s, ~800 MB/s) for NVMe on CM5 Compute Blades.
+---
+ installers/rpi5/src/main.go        |  10 ++++++++++
+ installers/rpi5/src/pcie-gen3.dtbo | Bin 0 -> 230 bytes
+ 2 files changed, 10 insertions(+)
+ create mode 100644 installers/rpi5/src/pcie-gen3.dtbo
+
+diff --git a/installers/rpi5/src/main.go b/installers/rpi5/src/main.go
+index fed3819..1134168 100644
+--- a/installers/rpi5/src/main.go
++++ b/installers/rpi5/src/main.go
+@@ -17,6 +17,9 @@ import (
+ //go:embed config.txt
+ var configTxt []byte
+ 
++//go:embed pcie-gen3.dtbo
++var pcieGen3Dtbo []byte
++
+ func main() {
+ 	adapter.Execute(&RpiInstaller{})
+ }
+@@ -52,6 +55,13 @@ func (i *RpiInstaller) Install(options overlay.InstallOptions[rpiOptions]) error
+ 		return err
+ 	}
+ 
++	// Write custom PCIe Gen 3 overlay for CM5 (its DTB lacks the pciex1 alias
++	// needed by dtparam, so we target pcie@1000110000 directly).
++	err = os.WriteFile(filepath.Join(options.MountPrefix, "/boot/EFI/overlays/pcie-gen3.dtbo"), pcieGen3Dtbo, 0o644)
++	if err != nil {
++		return err
++	}
++
+ 	if options.ExtraOptions.ConfigTxt != "" {
+ 		configTxt = []byte(options.ExtraOptions.ConfigTxt)
+ 	}
+diff --git a/installers/rpi5/src/pcie-gen3.dtbo b/installers/rpi5/src/pcie-gen3.dtbo
+new file mode 100644
+index 0000000000000000000000000000000000000000..863d0ea1bd8860dd361fe12d017330655d97a39e
+GIT binary patch
+literal 230
+zcmcb>`|m9S1H&^QwgBP-K&%18f<P<)#2}ys#2sK3D!~ZlG6QK|5Id<TIaensIoHVC
+z&<HBWm{ydSo|~Fi;$Q$40jU)QVs8D!icI~2<jhnDLjwZ?Ll6N`!N9;6AD>^AT9lJm
+z86OYQ1k%F-#Ntpk6Oe{s&gA^ug2a-{q?}ZSlEk9))Dm4FH-jNJu|hW|GcQ}WxF9t(
+Gg#iGv7$sN$
+
+literal 0
+HcmV?d00001
+
+-- 
+2.50.1 (Apple Git-155)
+